A memory controller may support a protocol used by the multiple memory modules coupled to a channel, such as the Joint Electron Device Engineering Council (JEDEC) Double Date Rate Third Generation (DDR) Synchronous Dynamic Random Access Memory (SDRAM) protocol, JEDEC SDRAM Low Power Double Data Rate 3 (LPDDR3), etc. Before using the memory channel, the memory controller configures the memory chips in the memory modules for operations.